Modern DRAM chips have many different voltages (e.g., more than 10) on-chip that have to be generated by a plurality of generator circuits. These voltages include several reference voltages (e.g., for receiver circuits and for bias current generation) as well as several voltages that supply various functional blocks on the chip with operating current (e.g., voltages for sense amplifiers and word line drivers). All of these voltages are generated from one external source voltage by the plurality of generator circuits.
There are basically three operating modes which occur for the voltage generating circuits. These modes are (1) a normal operating phase, (2) a test and burn-in phase, and (3) a power-on phase. In each of these modes the generator system operates in a different way, and needs to be controlled in a specific way. A controller for the generator system has to ensure a proper coordination of all generator functions for each of the various modes. More particularly, once the external source voltage (VEXT) is applied to the DRAM chip, the generator system goes through a power-on phase. After the power-on phase, all voltages on the DRAM chip are stable, and the generator system (and the whole chip) enters the normal operating phase. For burn-in and for test purposes, a multitude of additional functions have to implemented into the generator system.
The problem is that the overall logic behavior of the generator system, and its controller, is relatively complex. This is especially true during a late phase of a design project as all of the sub-systems are being put together, and it is very likely that changes in the logic functionality of the controller have to be made. In a current 1 Gigabit (GB) chip, known by the designation ZEUS DD1, logic control functions of a generator system therein were clearly separated from the voltage generating functions. The logic behavior of the generator system is implemented in a digital controller (a finite state machine). In order to realize a finite state machine, design and layout synthesis was used in the 1 GB Dynamic Random Access Memory (DRAM) chip. The logic behavior therein was specified in a truth table, and the concept was to create circuitry automatically within a short time by using the respective software tools. Thus, changes or corrections of the controller could theoretically be performed within a few hours, even in a late stage of a project.
Problems in existing solutions are that both design and layout synthesis tools do not provide a required solution to many problems for providing a flexible and fast controller design. For example, the design synthesis tool demanded a large amount of time for learning the handling and functionality of the tool, and this tool made manual corrections and working around of problems necessary. The layout synthesis tool created results that contained errors and required manual inspections and corrections. Additionally, one could not provide timing constraints to inputs to the tool for generating certain voltages which required manual checks of a synthesized layout for a critical path which then required manual corrections. Still further, when a controller is reset, its output signals are not well defined. Therefore, it is desirable to provide a technique where changes in the logic behavior of the controller is obtainable in a systematic and very quick manner and permit its output signals to be well defined during a resetting of the controller.
The present invention provides a controller circuit for a generator system that is very flexible so that its functionality can easily be adjusted to a specific generator system to allow for last minute changes of the behavior of a generator circuit, and permit well defined output signals during a resetting of the controller.